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In 1965, Gordon Moore, co-founder of Intel, made the observation that the number of transistors per square inch on integrated circuits had doubled every year since the integrated circuit was invented. He predicted that his trend would continue, and his observation became known as Moore’s Law.
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Imec and IBM engineers have been independently working to develop cutting-edge techniques to augment manufacturing processes that would allow the next decade’s chips to maintain the performance traditionally seen with Moore’s Law. These new processes would unite silicon wafers and unique materials, such as compound semiconductors made up from elements from column III and V of the periodic table. Both companies have built efficient transistors with the III-V semiconductor gallium arsenide. This transistor is highly efficient because it allows electrons to move through the material six times faster then silicon. This high level of efficiency allows the transistor’s operating voltage to be decreased while still maintaining the amount of current flowing through it, resulting in lower power usage.
Imec’s engineering team announced last November that they had taken an industry-standard 300-millimeter silicon wafer and formed fin-shaped field-effect transistors. FinFET’s are a type of 3D transistor deployed in the most advanced microprocessors. Imec creates its FinFETs by etching trenches into a silicon wafer that are only tens of nanometers wide. The trenches are filled with indium phosphide before indium gallium arsenide is added to produce the protruding transistor fin. Trenches reduce crystal defects in the transistor channel. Depositing indium phosphide on silicon leads to defects due to the 8 percent difference in the average spacing of the atoms in the two crystals. These defects terminate at the trench walls, enabling the growth of high-quality material near the wafer surface. Aaron Thean, director of Imec’s R&D program, does not, “want to claim that [the channel] is completely deflect-free, but it’s definitely good enough for the transistor to work now.”
Engineers at IBM are using completely different processes. They begin by forming a substrate composed of a 6nm thick film of indium gallium arsenide and an 8nm thick layer of silicon germanium, separated by a thin insulator. The silicon germanium allows for CMOS circuits to be produced because it enables the formation of high-speed transistors based on the movement of holes. IBM has demonstrated for the first time a hybrid, high-mobility CMOS circuit on an insulator. These formulated substrates offer three major benefits for integrated device manufacturers. First, very low leakage currents, due to the insulating layer beneath the device. Second, minor adjustments to the foundry processes because the challenges of introducing new materials are shifted to the substrate supplier. And lastly, there is a large amount of freedom for the circuit designer to select the size and position of the transistors.
Researchers at IBM’s T.J. Watson Research Center, in Yorktown Heights N.Y., have a device that they claim is better than silicon, if they compare the same dimensions. Yanning Sun of IBM Watson has detailed the results of indium gallium arsenide transistors with a 30nm gate length, which is about the dimensions of a state of the art transistor from 2010. IBM Watson and Imec engineers will now attempt to shrink their transistor dimensions to allow a true comparison.
[i] http://www.webopedia.com/TERM/M/Moores_Law.html
http://spectrum.ieee.org/semiconductors/materials/compound-semiconductors-join-the-race-to-sustain-moores-law
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