. The earliest forms of device testing were geared to laboratory work, with an electrical engineer peering through a microscope and manually positioning a few electrical probes on the surface of a device. The probes would be connected to a collection of power supplies, meters, and perhaps an oscilloscope.
This approach, called “rack and stack”, does not lend itself to mass production as it is both slow and an inefficient use of an expensive engineer’s time. By the late 1950s, companies began producing integrated pieces of test equipment, and by the early 1970s tools (“testers”) that combined all the separate equipment into a single box that could be programmed to apply stimulus to a device and measure the response therefore creating ATE. In 1972 Advantest Japan announced its T320/20 LSI tester .
Two other pieces of the puzzle were the creation of the probe card and the wafer prober. The probe card is, at its heart, a printed circuit board (PCB) with electrical probes in precise positions to match the connection points on the individual device to be tested. The PCB, at one end, holds the probe tips precisely in a “probe array”. At the other end, it has an electromechanical interface to the tester. In the beginning, testers connected to probe cards via cables and connectors.
The wafer prober is a specialized robot. Its purpose is to move a wafer full of devices to be tested beneath a stationary probe card – die by die – and then bring the wafer into contact with the probe card. This was an essential step in the move to true mass production of semiconductor devices. Electroglas introduced the first commercial prober for testing semiconductors (the EG 900) in 1964 . The prober has the mechanical challenge of handling wafers with very high precision and registering them to a probe card that is mounted within it (Roberts 13).
Testing System Evolution
The basic system challenges have remained the same for the last 50 years. Figure 1 shows an example of a system diagram for a wafer test implementation.
Figure 1: Basic Wafer Test System
Figure 1 shows the 4 major components of the classic test system; the tester, the electromechanical interface between the tester and the probe card, the probe card, and the prober. [Of course, you need wafers or the whole system is pointless, but I’ll leave them for the subject of a future blog]
Automatic Test Equipment Evolution
ATE have had to keep pace with the constant size reduction of devices and the need for more and more test lines at higher and higher speeds. Modern testers now have to contend with hundreds of signal pins at GHz speeds and supply multiple power sources for CPUs and GPUs that suck current in amps. The need for speed and power has rippled through every other piece of the system. Modern systems can supply up to 1024 test lines that can run at GHz switching speeds.
Electromechanical Interface Evolution
The EM interface is the “extension cord” that connects the tester to the probe card. It provides a way to quickly connect and disconnect the two big elephants (tester and prober) and also provides a “consumable” component that protects delicate contacts on expensive testers and probe cards.
When there were only a handful of signal and supply lines and the maximum test speed was less than 10 MHz, it was OK to connect the tester to the probe card with long cables and connectors. This “cable-out” technique ran into trouble when the test speeds started to go above 100MHz. At that point, even the best coaxial cable begins to look lossy and provides unacceptable levels of delay. The next advancement was the creation of the POGO tower.
Figure 2: POGO™ Tower Interface
Figure 2 shows a typical Tester-to-Probe Card interface, widely in use today. The Device Under Test (DUT) interface converts the form factor of the connection points in the tester to a more standard connection pattern that matches the connection pattern on the probe card. Initially, DUT interface boards were just space transformers but in modern systems, additional components are placed there to provide signal pre-conditioning specific to the device being tested . Figure 3 shows a typical system setup.
Figure 3: Typical POGO™ Interface. Image courtesy of Advantest
The POGO™ tower is a mechanically precise arrangement of spring contacts, top and bottom, with controlled-impedance connections in-between. Since the mechanics and electronic characteristics of the tower are well known, the test system can compensate for insertion losses and signal. For the latest high-performance device applications, POGO™-based interconnects have run out of gas.
The limiting issues for POGO™ schemes are path length and signal transitions. A POGO™ tower adds upwards of 4 inches to the signal path length, but the bigger issue is the number of physical connection points between the tester pins and the probe card. Each point is a discontinuity with an insertion loss. Now that supply values are in the 1.2V range, the difference between logic high and low is measured in 10s of millivolts and the connection losses just eat away at the total budget.
The latest change to interface schemes is the all-in-one DUT interface/probe card that is a game changer in terms of the knock-on implications to prober and equipment designers. I’ve been designing automatic test equipment and tester interfaces for the semiconductor industry for most of my career and this change has presented some of the most interesting engineering challenges I’ve encountered in a long time.
Check out my previous blog on Advantest shipping it’s 1,000th test system http://www.glewengineering.com/blog/bid/105274/Semiconductor-Test-Equipment-Supplier-Reaches-Huge-Milestone
Published Oct 24, 2014.
Next: Tester-Prober Interfaces: Direct Probe (Part 2)
 https://www.advantest.com/US/AboutAdvantest/History/index.htm  http://www.electroglas.com/company/history.shtml  Roberts, Gordon, and Mark Burns. An Introduction to Mixed-Signal IC Test and Measurement. New York: Oxford University Press, 2001. Print.  http://www.evaluationengineering.com/articles/201107/reducing-the-cost-of-test.php
Next: Direct Probe and the System Interface Implication