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IC Thermal Management: Electronic systems reliability & power cycling

  
  
  
  
  

PCB on fire

 

                  Device reliability under changing temperature is one of the most difficult tasks when packaging semiconductor devices.  A typical test involves subjecting a packaged device to 0 - 100 degree C  temperature range, with residency times designed to induce a suspected failure mode.  Standard temperature  cycling tests can be performed inexpensively in large scale allowing for good testing statistics.  Typically, component (IC) manufacturers use this test during development phases when exploring new packaging configurations. LED manufacturers and MEMs manufacturers can utilize this method.

                  The product companies, which deliver directly to consumer, attach high importance to testing the system as a whole, as opposed to just a package or semiconductor power cycling.  Power cycling becomes one of typical system tests.  Power cycling involves powering the whole system in a cyclical manner to look into most vulnerable failure modes, majority of which are associated with the modulated CTE mismatch driven stresses.  While seemingly simple in concept, thermal management of devices plays key role on performing this out-the-door sanity check: without a heat sink, for example, device operation may not be possible at all.   

                  Stated simply, the thermal solution must ensure the same temperature envelope during the field operation that the component was tested for.  If a component, i.e. CPU, underwent testing between 0 and 100 C, as an example, thermal solution must be able to keep the device operation in this temperature envelope.  While as usual, complications arise, one can state to the first order (combined electro-thermal failure modes use different testing protocols) that power cycling from thermal perspective is the test of thermal solution. 

                  Second important effect that needs testing is the added mechanical loads from putting the component in to the system: they may induce a stress field different from when testing components.  An example is the case of BGA packaging. where additional CTE-mismatch driven effects are introduced at board assembly.  This scenario can still be accounted for by the component maker when testing assembled boards in temperature cycled environment. 

                  There is a gap between power and temperature cycling test, which can be substantial.  Temperature cycling, mostly developed as a quick way of looking into field reliability, could be either too constrictive leading to over-engineered and costly manufacturing or not be able to screen out all potential field failures which is an even worse of a scenario.  Power cycling tests can be difficult to set up and configure.  Temperature cycling is rather straight forward.

                  Power cycling is usually the domain of reliability engineers.  Different engineering disciplines can function as reliability engineers.  Generally, mechanical engineers, materials engineers, and electrical engineers perform these functions. 

                  There are certain material sets that were developed using power cycling reliability as opposed to intermediate step of temperature cycle testing. This type of development activity is costly due to having to develop power cycling equipment needing precise control of power delivery and dissipation as well as accurate thermal characterization.  Glew Engineering can assist with your efforts on developing cost-effective reliable electronics, reliability engineering, and power cycling.

 

 

 

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

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Linear v Novellus (Semiconductor Equipment)

  
  

After 8 long years, Novellus finally rid itself of the lawsuit with Linear Technology. Irell and Manella LLP, for whom Glew Engineering has worked in the past, took no prisoners in the unanimous jury verdict announced yesterday in favor of their client Novellus.  The jury consisted of 12 men and women in Santa Clara, CA, the heart of the silicon valley.  Certainly good news for Novellus' legal team, as well as their bottom line. Congratulation to Jonathan Kagan Esq. and his colleagues.  Now both sides can get back to what they do best - making chips and chip equipment.

Novellus' also shipped their 1000th Vector PECVD tool in February? Considering the tool's throughput and uptime, there may be as many chips out there by now with Novellus' dielectric films as those of any semiconductor equipment manufacturer. See the details at: 

http://ir.novellus.com/releasedetail.cfm?ReleaseID=441840

 

Semiconductor Equipment, Glew Engineering

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