EDA methodology Perl script for Verilog file to list the pin signals
We have attached a PERL script which will accept a Verilog file and a Pin from the user on the command line and will report on the signals attached to the pin. Let us know what you think. This sort of script can be very useful to the electrical engineering designing integrated circuits, IC, using electronic design automation, EDA. Glew Engineering can help you with your EDA methodology by providing tools that can make your engineers more efficient. The cost of the EDA software, engineering workstation, and the engineer, can be rather high. It is important to keep them as efficient as possible.
Glew Engineering Consulting's experts in EDA methodology can assist with your CAD EDA systems: Cadence(TM), Synopsys(TM), Mentor Graphics (TM) and more.
The command line PERL script for use in EDA CAD for semiconductor engineering of integrated circuits (IC) and ASICS is fully functional and yours to try out. This is just a small sample of the many ways in which we can help with your EDA needs for semiconductor IC design. Contact Glew Engineering to discuss your CAD EDA, or any engineering work your business requires.
foreach( MyTerminal cv~>terminals
fp = outfile("PININFO.1" "w")
if(cv = dbOpenCellViewByType(libid dbCell~>name "symbol" "" "r") then
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