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Colorful Diamonds to Benefit the Semiconductor Industry

 

colored diamondsWhile they may be flawed due to their color, colorful diamonds are among the most sensitive detectors of magnetic fields known.  University of California, Berkeley, physicist Dmitry Budker, Ron Folman of Ben-Gurion University of the Negev in Israel, and colleagues from UCLA have demonstrated how diamond sensors can measure tiny magnetic fields in high-temperature semiconductors.  While high-temperature semiconductors were discovered in the late 1980s, and their discoverers won the Nobel Prize, they are not yet truly understood.  “Diamond sensors will give us measurements that will be useful in understanding the physics of high temperature superconductors,” Budker said. 

High-temperature semiconductors are mixes of materials like yttrium or bimuth.  When cooled to -170 degrees Celsius they loose all resistance to electricity.  Low-temperature semiconductors on the other hand have to be chilled to just several degrees above absolute zero.  When high-temperature semiconductors were discovered in 1987, it was predicted that room-temperature semiconductors would be a reality in the near future.  Room-temperature semiconductors could lead to lossless electrical transmissions or magnetically levitated trains.  Neither has yet to be a reality.  Colorful diamond sensors could allow researchers to take steps forward to making room-temperature semiconductors a reality. 

Colorful Diamonds

Colored diamonds range from yellow and orange to even purple.  The color comes from flaws in the gem’s carbon structure.  Some of the carbon atoms have been replaced by an element, such as boron, that emits or absorbs a specific color of light.  After scientists learned that they could create synthetic diamonds, they found they could alter a diamond’s optical properties by injecting impurities.  Budker, Folman, and their colleagues bombarded a synthetic diamond with nitrogen atoms to displace some of the carbon atoms, leaving left holes in some places and nitrogen atoms in others.  The crystal was then heated, forcing the holes to move and pair with nitrogen atoms, leaving a diamond with a nitrogen vacant center.  The amount of light the negatively charged centers re-emit when excited with light becomes sensitive to magnetic fields, allowing them to be used as sensors that are read out by laser spectroscopy.  Folman noted that they color centers in diamonds uniquely exhibit quantum behavior, whereas most other solids at room temperature do not.  “This is quite surprising, and is part of the reason that these new sensors have such a high potential,” Folman said.

Possible Applications

Researchers hope that nitrogen-vacant centers will be able to probe for cracks in metal, such as bridge structures or jet engine blades, be the building blocks for quantum computers, or even have homeland security applications.  Budker works on sensitive magnetics filed detectors, and Folman builds atom chips to probe and manipulate atoms, so they have focused on using these magnetometers to study new materials.  “These diamond sensors combine high sensitivity with the potential for high spatial resolution, and since they operate at higher temperatures than their competitors – superconducting quantum interference device, or SQUID, magnetometers – they turn out to be good for studying high temperature superconductors,” Budker said. “Although several techniques already exist for magnetic probing of superconducting materials, there is a need for new methods which will offer better performance.”  This team of researchers used the diamond sensors to measure properties of a thin layer of yttrium barium copper oxide (YBCO), which is one of the two most popular types of high-temperatures superconductor.  The diamond sensor was integrated with the superconductor on one chip and used it to detect the transition from normal conductivity to superconductivity.  Tiny magnetic vortices, which appear and disappear as the material becomes superconducting, were also detected. 

“Now that we have proved it is possible to probe high-temperatures superconductors, we plan to build more sensitive and higher-resolution sensors on a chip to study the structure of an individual magnetic vortex,” Folman said. “We hope to discover something new that cannot be seen with other technologies.”  Researchers are looking into other areas that could benefit from magnetic sending.  The possibilities are limitless.

 

Sanders, Robert. "Colored Diamonds Are a Superconductor’s Best Friend." UC Berkeley NewsCenter. N.p., 6 Mar. 2014. Web. 17 Apr. 2014.

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

Basics of Chemical Vapor Deposition in the Semiconductor Processing Industry

 

SemiconductorIt is believed that the German chemist, Robert Bunsen, documented the first account of the manufacturing technique known as chemical vapor deposition (CVD) in 1852.  He did so while observing that iron oxide condenses as crystals from hot volcanic gases containing hydrogen chloride.  While at the time Bunsen was more concerned with the phenomenon than in the materials synthesis, a few years later St. Claire de Ville became the first scientists to put CVD to use when he formed oxides of magnesium, titanium, and tin.[i]  CVD has gone on to become a widely used industrial tool that produces a vast range of materials, especially in the semiconductor processing industry.

While process engineers of the 1960s only had the option of atmospheric chemical vapor deposition, today’s engineers have many more options.  In the semiconductor industry, the term deposition refers to any process where a material is physically deposited on the wafer surface.  CVD is primarily used to deposit films on the wafer.  During the process, a chemical (C) containing the atoms or molecules necessary for the final film are mixed in a deposition chamber to form a vapor (V).  The atoms or molecules are then deposited (D) on the wafer surface to form a film.  Usually the addition of energy to the system is necessary for the process to take place.  This can come in the form of heating the chamber or the wafer itself.  The deposited film growth occurs in several specific stages, the first being nucleation.  Nucleation occurs as the first few atoms or molecules deposit on the wafer surface.  These initial atoms or molecules form islands that grow larger.  Next, these islands spread until they form a continuous film.  This is the transition stage.  During this stage the film has different chemical and physical properties then the final, thicker film.  After the transition film is formed, the growth of the final film begins. 

Basic CVD System Design

In general a CVD system has the same parts as a tube furnace: source cabinet, reaction chamber, energy source, wafer holder, and loading and unloading mechanisms.  With the chemical housed in the source cabinet, vapors are generated from pressurized gas cylinders or liquid source bubblers.  Pressure regulators, mass flow meters, and timers control the gas flow.  The deposition itself occurs in the reaction chamber.  The energy sources used are either heat, induction RF, radiant, plasma, or ultraviolet.  The chamber configuration and heat sources used determine the style and material of the wafer holder. 

Various CVD System Types

There are primarily two types of CVD systems: atmospheric pressure (AP) or low pressure (LP), however the most advanced device films are deposited in low-pressure systems.  Another variation of systems is either cold wall or hot wall.  In a cold-wall system the wafer holder or wafers are directly heated with induction or radiant heating, while the walls of the chamber remain cold.  This allows the reaction to occur only at the heated wafer holder.  Hot-wall systems heat the wafer, wafer holders, and the chamber walls, causing the reaction to occur throughout the chamber.  This leaves reaction products on the inside of the chamber walls, and thus requiring frequent cleaning to prevent wafer contamination.  CVD systems use primarily two energy sources: thermal and plasma.  Thermal sources include tube furnaces, hot plates, and RF induction.  Plasma, combined with lower pressure, offers the benefit of lowered temperatures and good film composition and coverage.  Additional benefits of low-pressure CVD include less dependence on gas flow dynamics, less time for gas phase reaction particles to form, and the process can be performed in a standard tube furnace. 



[i] http://www.electrochem.org/dl/interface/spr/spr98/IF3-98-Pages36-39.pdf

Van Zant, P. (2000). Microchip fabrication, a practical guid to semiconductor processing. (4th ed.). New York, NY: McGraw-Hill.

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

Ion Implantation in the Semiconductor Processing Industry

 

SemiDiffusion doping techniques were originally used in the semiconductor processing industry.  However, high-density circuits requiring smaller feature sizes, has moved the industry to use ion implantation as the primary dopant introduction technique.  Issues with thermal diffusion that placed limits on the production of advanced circuits included: ultra thin junctions, poor doping control, surface contamination interference, lateral diffusion, and dislocation generation.  Ion implantation overcomes these limits of diffusion.  During ion implantation there is no side diffusion, the process can take place at room temperature, dopant atoms are placed below the surface, and a wide range of doping concentrations are possible.  There is also greater control of the location and quantity of dopants put into the wafer. 

The same dopant elements that are used in the diffusion process are used in ion implantation.  However, while liquid, gas, or solid dopant sources are used in diffusion, only gas and solid sources are used for ion implantation.  Gases are used more often because they offer a higher level of control.  The gases are mostly fluorine based, such as phosphorus pentafluorid (PF5), arsenic pentafluoride (AsF5), or Phosphorus trifluoride (PF3). In certain applications, solid sources are used, such as phosphorus pentoxide (P2O5).  

Ions implanted are ionized atoms of the dopants.  Source vapors are fed into a low-pressure chamber where the ionization occurs.  Inside the chamber, a filament is heated to where electrons are created on the filament surface.  The negatively charged electrons are attracted to an oppositely charged anode in the chamber.  As the electrons move from the filament to the anode they collide with the dopant source molecules, thus creating positively charged ions.  A cold-cathode technique is another ionization method.  In this method, a high-voltage electric field is created between a cathode and anode, which created the electrons.

The next step is ion selection, and occurs in a mass analyzer.  This subsystem was developed during the Manhattan Project and used while developing the atomic bomb.  The analyzer creates a magnetic field and the species leave the ionization subsystem traveling at a high rate of speed.  Each of the positively charged species is bent in an arc, with a radius determined by the mass of the particular species, its speed, and the strength of the magnetic field.  A slit at the end of the analyzer allows only one species to exit, the desired ion. 

Once the analyzing subsystem in complete, the ion moves into an acceleration tube.  This subsystem is designed to accelerate the ion to gain sufficient momentum to penetrate the wafer surface.  The necessary momentum is obtained by utilizing the fact that negative and positive charges attract each other.  The acceleration tube is linear, with annular anodes along its axis.  Each anode is negative in charge, with the charge amount increasing down the tube.  Once the positive charged ion enters the tube it accelerates long the tube.  The voltage value is determined based on the mass of the ion and the momentum required at the wafer end of the implanter.  A higher voltage leads to higher momentum and thus allowing the dopant to be implanted faster and deeper. 

Success ion implantation relies on the implantation of only the desired dopant atom.  Dangers include the possibility of residue molecules in the system ending up on the wafer surface as well.  While ion implantation is still faced with numerous challenges, it allows for the production of advanced circuits in the semiconductor processing industry.      

 

Van Zant, P. (2000). Microchip fabrication, a practical guid to semiconductor processing. (4th ed.). New York, NY: McGraw-Hill.

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

Interacting With Printed Sensors

 

Below is an article written by one of our semiconductor processing experts, Dr. Michael Watts.

If there is one feature that distinguishes all our modern portable devices from the traditional PC (a wonderful concept—the “traditional PC”), it’s the way we interact. Separate keyboards are done. It’s all touchscreens on pretty much everything, along with other sensor opportunities.

There are many uses for the built-in cameras in cell phones from videoconferences to anything Messrs. Weiner and Rivera can imagine. A more useful approach is to deduce information about the user. For instance, cell phones can identify when you look away fron the screen and pause a video, presumably using the camera. I am not convinced how useful a feature this is, seeing as I do not watch long videos on my pad, but it is a great starting point for a new capability. The non-contact swipe is another interaction detected by the camera sensor. In the future, stereo cameras could be used to provide distance sensing and are obviously low enough cost these days.

Making the surface of a portable device into a multifunctional surface is a great application for flexible electronics, because large area, low cost, thin, and flexible are all desirable. Some of the ideas discussed in detail at the Printed Electronics Conference “ IDTech” in Berlin, were improved touchscreens, large area infrared photocells, and surfaces that provide feedback from both the front and back of the device.

The latest touchscreens are built into the front surface of the display. “In-Cell” is the Synaptics version. The sensor is a set of transparent crossbars, and the contact of a finger or other conductive object changes the capacitance of the sensor. The built-in sensor means fewer pointing errors when you touch a button on the screen as compared to a stuck-on overlay. An indication of some of the complexities was shown in a report from TI that heat from fingers can mislead a touchscreen.

touch 300x166

Synaptics In-Cell Touch Screen Strategy




Further improvements to touchscreens need higher conductivity bars, more flexible materials, and more transparency. The most popular materials strategy is to use composites with conductive nanofibers. Cambrios are focusing on silver fibers that produce a film with 5 ohm per square resistance. The narrow wires improve transparency.

Large area pressure sensors are being developed by Tactonic. They creating an array of small bending plates so that the complete shape of the pressure source can be deduced. They see an opportunity for all sorts of shaped sensor surfaces such as steering wheels, or cell phone backs.

The idea of large area transparent infra-red photocells to detect both contact and proximity touch is being developed by Isorg. They use an organic semiconductor so that the devices are transparent.

Providing mechanical feedback on a transparent surface would really improved interaction with the device. Numerous studies have shown that tactile feedback improves interaction. One approach uses piezo electrical materials that change shape under electrical voltage. The most effective materials are derivatives of poly(vinylidine chloride)—PVDF. Oriented PVDF molecules have a strong dipole, which creates changes in molecular shape under electric fields. Strategic Polymer Systems has built PVDF copolymers and composites that will generate 5% strain in a rigid film—enough to create a mechanical motion that can be easily detected by a fingertip.


For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

Multilayer Photoresist Processing

 

describe the imageA basic ten step lithography process is based on a single photoresist layer, and assumes that the layer can resolve the necessary images without pinholes or failing during the etch process.  The sub-micron era has made variations to the single resist layer process necessary. 

 

With numerous multilayer resist processes available, the choice depends on the size of the resist opening and the severity of the surface topography.  A multilayer resist process features a thicker bottom layer that fills in the valleys and planarizes the surface.  The image is first formed in a layer of photoresist on the top of the planarizing layer.  Surface imaging allows small dimension imaging because the surface is flat.  Two layers of photoresists, each with different polarity, are used in a dual multilayer resists process.  This process can resolve small geometries on wafers with a varied topography.  In the first step, a relatively thick layer of resist is applied and baked to the thermal flow point, with the goal of achieving a planar top resist surface.  The typical multilayer process will use a positive-acting polymethylmeth acrylate resist sensitive to deep ultraviolet radiation.  Secondly, a thin layer of positive resist sensitive to just ultraviolet radiation is spun on top of the fist layer and processed.  This thin top layer allows the resolution of the pattern without the adverse effects of thick resist layers or reflections from steps in the surface.  The top layer of resist, which conforms to the shape of the bottom layer and is referred to as a conformal layer, acts as a radiation block, leaving the bottom layer unpatterned.  The wafer is then given a blanket of ultraviolet exposure, which exposes the underlying positive resist through the holes in the top layer, thus extending the pattern down to the wafer surface.  A development step completes the hole resolution and the wafer is ready for etch.

 

The two photoresists are chosen based on compatibility throughout the process, reflection problems from the subsurface, standing waves, and sensitivity problems with PMMA resists.  Also, the two resists used must have compatible bake processes and independent developing chemistries. 

 

Variations of the basic dual-level resist process include dyes in the PMMA and the addition of antireflection layers under the first resist layer.  The dual-level process can be used for various outcomes.  One use is as a lift-off technique.  An overhang can be created, that assists in the clean definition of the metal line on the surface, by adjusting the development of the bottom layer. 

 

A trilevel resist process includes a hard layer between the two resist layers.  The hard layer can be a deposited layer of silicon dioxide or other developer-resistant material.  Similarly to the two layer process, the image is formed in the top photoresist layer.  Etching then transfers the image into the hard layer.  The final step is the formation of the pattern in the bottom layer, using the hard layer as an etch mask.  The hard intermediate layer allows for the use of a nonphotoresist bottom layer.

Van Zant, P. (2000). Microchip fabrication, a practical guid to semiconductor processing. (4th ed.). New York, NY: McGraw-Hill.    

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

S-FIL for Sub-80nm Contact Hole Patterning

 

Below is an article orignially published by Sold State Technology Magazine. One of the athors is our own lithography expert, Dr. Michael Watts.

Reliable printing of sub-80nm contact holes is a challenge that manufacturers of state-of-the-art DRAM and MPU devices must overcome within the next few years. Step-and-flash imprint lithography (S-FIL) has already demonstrated the ability to resolve sub-30nm lines in previous studies. Here, the first commercially available step-and-repeat imprint tool is used to show the ability of S-FIL to repeatably print dense arrays of sub-80nm contact holes.

Currently, 193nm lithography is being integrated into production fabs around the world to manufacture state-of-the-art silicon devices. At the same time, however, the future of lithography beyond the 193 horizon is not at all clear. What technology will establish itself as the heir apparent to 193? Immersion lithography applied at 193nm, 157nm lithography, and extreme ultraviolet lithography (EUVL) each have promise. However, immersion lithography is still in the early stages of development, and the time for introduction of EUVL is still several years away. In recent months, even the future of 157nm lithography has had considerable doubt cast upon it by Intel's announced decision not to install this technology in any of its fabs.

The International Technology Roadmap for Semiconductors (ITRS) has outlined concrete goals for critical dimensions (CD) needed to maintain the advance of memory and microprocessor units (MPU). The schedule defined by ITRS for contact holes is quite aggressive. For 2003, ITRS calls for a contact-hole CD in resist of 122nm and only 75nm by 2007. Due to the shape of contact holes and the poor aerial image created in projection lithography, they are by nature difficult to resolve. In addition, trim etches routinely used to further reduce the CD of gate resist lines cannot be applied to contact holes. As a result, nanoimprint technology, with its inherent independence from aerial image constraints, may become an important option for meeting this challenge.

Contact holes1

An engineer looks inside the Imprio 50, a sub-50nm Step-and-Flash imprint lithography (S-FIL) tool. (Courtesy Molecular Imprints Inc)

Several nanoimprinting techniques are being actively developed as alternative approaches to optical nanolithography. Imprint lithography is essentially a micromolding process in which the topography of a template defines the patterns created on a substrate. Investigations by Motorola Labs and others have shown that the resolving potential of imprint lithography is only limited by the resolution of the template fabrication process [1–5]. These techniques possess important advantages over photolithography and other next-generation lithography (NGL) techniques since they do not require expensive projection optics, advanced illumination sources, or specialized resist materials. As a result, nanoimprint lithography has the potential to offer a significant cost-of-ownership reduction when compared to other NGL methods such as EUVL [6].

Step-and-flash imprint lithography

Invented at the U. of Texas at Austin [7], S-FIL is one of the new methods of nanoimprint lithography being actively developed. As with other nanoimprint methods, S-FIL has been shown to be capable of sub-30nm resolution [4]. The process, depicted in Fig. 1, uses a transparent template containing the pattern to be printed etched into its surface:

1. Using a precise piezo-driven dispense head, a silicon-rich, low-viscosity, photocurable, monomer solution is dispensed onto the substrate in the region where the pattern is to be printed.
2. The template is then pressed into contact with the wafer using very low pressures (<1psi) to spread the liquid across the field and fill the template's relief.
3. UV light is irradiated through the back of the template, curing the monomer.
4. The template, pre-coated with a fluorocarbon release agent, is removed, leaving the cured, patterned resist layer behind.
5. Finally, a breakthrough etch passing through the residual etch barrier and a transfer layer (any organic spin-coated resin such as an antireflective coating, ARC) transfers the high aspect ratio pattern to the substrate.

Contact holes2

Figure 1. Process flow for step-and-flash imprint lithography [8]. The silicon-containing etch barrier monomer is applied in a) and the cured barrier layer is used as a mask for etching in e).

Many challenges remain before S-FIL can be considered for integration into any type of manufacturing environment. These result from two factors common to all imprinting lithographies: 1) each has a basis in contact printing (although for S-FIL, a key difference is that a low-viscosity liquid is present between template and wafer, creating a "lubricated" process), and 2) each uses masks (templates) that are sized at 1×. With contact printing comes the potential to generate and propagate defects. Therefore, the durability for printing thousands of defect-free die without template cleaning or maintenance must be demonstrated. In addition, overlay and distortion correction issues must be solved for a transparent template.

However, it is likely that the mask industry itself would feel the greatest effect. Any move toward a 1×-based lithography will accentuate the need for fast-writing, high-resolution pattern generation capable of extremes in both pattern placement accuracy and CD control. Additionally, an entirely new emphasis on cleaning, inspection, and repair of templates would be required since, in imprint lithography, there is no analogy to pellicles. In short, a whole new level in maskmaking infrastructure would need to be established.

S-FIL Template Fabrication

The fabrication methodology used for S-FIL templates is similar to that used to manufacture phase-shift masks. A chromium film 15nm thick is first sputtered onto a standard 6 × 6 × 0.25 in. (6025) quartz mask blank. The plate is then coated with ZEP 520A positive e-beam resist, and exposed using a Leica VB6 electron-beam exposure system operating with a beam accelerating voltage of 100keV. Following development, the resist mask is used to pattern the chrome layer, after which it is stripped in a piranha bath. The chromium layer is next used as a hard mask to etch into the quartz substrate to a depth of ~100nm. The chrome layer is stripped, leaving an all-quartz template. Finally, the active printing area (a 25 × 25mm square) is formed into a pedestal by etching back the surrounding region using a separate patterning step and a timed, wet hydrofluoric acid etch. Templates are diced from the 6025 blank quartz plate to their final external dimensions of 65 × 65mm using a diamond saw.

Contact holes3

Figure 2. a) Template resist image of 80nm design pillars, pitch 1:2, actual CD = 72nm; and finished template images of b) 80nm design quartz pillars, pitch 1:2, actual CD = 51.2nm; and c) 80nm, 1:1 pitch pillars after 20 consecutive wafer prints (740 die).

Printing contact holes using S-FIL requires an array of pillars — a worst-case structure from the point of view of template wear — to be fabricated on the template. ZEP 520A resist offers extremely high contrast for this task, enabling pillars with as much as a 4:1 aspect ratio (Fig. 2a) to be resolved. However, two factors make achieving sub-100nm target CDs especially challenging: Proximity effects are significant, and so the pillar CD depends strongly on the designed pitch. For a given exposure dose, as the pitch increases (space between pillars widens), the resulting pillars are biased smaller. Complicating matters further, the development of features smaller than 100nm is highly nonlinear with dose, and so a pillar array can be completely cleared by only a slight over-exposure. Figures 2a and b show an array of pillars with a 80nm design size and a 1:2 pitch a) after resist develop and b) for the final template. The resulting pillars measure only 72nm due largely to proximity effects. Figure 2c shows a defect-free array of 80nm pillars having a pitch of 1:1 imaged after 20 wafer prints (740 die).

Wafer prints

Contact holes4

Figure 3. 80nm design contact-hole array, 1:1 pitch, CD = 66nm: a) wafer #1 of 10-wafer series; b) wafer #10.

All imprinting was done on 200mm silicon wafers using an Imprio 100 system manufactured by Molecular Imprints Inc. (MII), Austin, TX. Prior to imprinting, wafers were coated with a 600Å planarizing layer of Brewer Science DUV30J ARC. MII cleaned and coated the template with a fluorocarbon release material using a proprietary process. For these tests, 10 wafers were run consecutively with 37 fields printed on each wafer. During the tests, the template was not cleaned or altered in any way, or removed from its chuck. Figure 3a shows a printed array of contact holes measuring approximately 66nm dia. This array was the result of a pillar array on the template designed at 80nm with 1:1 pitch. A bias of about 7–10nm between pillar and printed contact was measured, which may be a result of some sloping of pillar sidewalls. Figure 3b was taken on the 10th wafer of a consecutive series of prints. This field, the 370th in the series printed, shows no discernable degradation compared to 3a, which was imaged from the first wafer printed. Before this experiment, there was considerable concern about the fragile nature of sub-100nm pillars having an aspect ratio in excess of 1.0. It was not known whether these structures would withstand the shearing forces, however minute, they may encounter during the printing and releasing process. The tests did much to allay these fears, showing both the robustness of the template and the gentle nature of the printing process.
Contact holes5

Figure 4. a) Cross-sectional SEM of 100nm contact holes, pitch = 1:1, top CD = 89nm; b) cross-sectional SEM of 80nm contact holes, pitch = 1:1, top CD = 72nm.

Figure 4 depicts cross-sectional SEM micrographs of printed contacts in the etch barrier layer. Figure 4a shows contacts created by a 100nm (1:1 pitch) template pillar array, measuring 89nm at the top and approximately 60nm at the bottom, reflective of the slope in template sidewalls. Figure 4b shows contacts created by an 80nm (1:2 pitch) template pillar array, measuring 72nm at the top and approximately 49nm at the bottom. Completion of this process with transfer of contact holes down to the substrate will require both a breakthrough etch of the residual layer and a transfer layer etch. Work on these etch processes is proceeding at the U. of Texas at Austin and at Motorola Labs [9].

Conclusion

Step-and-flash imprint lithography has made considerable progress in a very short time, overcoming many important technical hurdles along the way. The first commercial step-and-repeat imprint tool has shown the ability to print sub-80nm contact hole arrays. No apparent degradation in printing quality was noted following almost 400 consecutive imprints. Given the inherent difficulty of printing contacts using optical methods, it may turn out that a nanoimprint method such as S-FIL may be called upon to meet this challenge. Achieving success will require a combined effort not only from S-FIL processing and tooling engineers, but from mask fabricators as well. Producing high-quality 1× templates for S-FIL will be, without question, a considerable challenge for the mask industry in the era of sub-100nm linewidths. However, it seems assured that mask production will be dramatically more difficult for fabricators and more costly for users regardless of which NGL technology is ultimately adopted.

Acknowledgments

The authors would like to thank Kevin Nordquist, Bill Dauksher, Kathy Gehoski, Eric Ainley, Adolpho Rios, Jeff Baker, Eric Newlin, Gene Rossi, Ted Gehoski, and David Standfast for their work in processing S-FIL templates; Lester Casoose and Mark Madrid for providing SEM analysis; Ron Voisin, Phil Schumaker, Ian McMackin, Frank Xu, Van Truskett, Chris Mackay, and Ecron Thompson for their contributions; and Laura Siragusa and Vida Ilderem for their support in this work. This work was partially funded by DARPA (N6601-02-C-8011, N6601-01-1-8964).

References

1. Y. Xia, G.M. Whitesides, Angew. Chem. Int., 37, pp. 550–575, 1998.
2. S.Y. Chou, P.R. Krauss, P.J. Renstrom, J. Vac. Sci. Technol. B, Vol. 14(6), pp. 4129–4133, 1996.
3. M. Otto, M. Bender, B. Hadam, B. Spangenberg, H. Kurz, Microelectronic Engineering, Vol. 57–58, pp. 361–366, 2001.
4. D.J. Resnick, et al., "High Resolution Templates for Step-and-flash Imprint Lithography," Proc. of SPIE, Vol. 4688, pp. 205–213, 2002.
5. M. Colburn, et al., "Step-and-flash Imprint Lithography for Sub-100nm Patterning," Proc. of SPIE, Vol. 3997, pp. 453–457, 2000.
6. S.V. Sreenivasan, C.G. Willson, N.E. Schumaker, D.J. Resnick, "Cost Analysis of Step-and-flash Imprint Lithography," Proc. of SPIE, Vol. 4688, pp. 903–909, 2002.
7. M. Colburn, et al., "Step-and-flash Imprint Lithography: A New Approach to High Resolution Patterning," Proc. of SPIE, Vol. 3676, p. 379, 1999.
8. T.C. Bailey, et al., "Recent Advances in Step-and-flash Imprint Lithography," Interface 2002.
9. S.C. Johnson, et al., "Advances in Step-and-flash Imprint Lithography," Proc. of SPIE, Vol. 5037, pp. 197–202, 2003.

Solid State Technology February, 2004 Author(s) : David Mancini Douglas Resnick S.V. Sreenivasan Michael Watts

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

Semiconductor Processing: Development Methods

 

ChipOnce a semiconductor wafer has completed the alignment and exposure step, the device or circuit pattern is developed in the resist.  Development techniques are designed to leave an exact copy of the mask or reticle pattern in the resist layer.  Below we will discuss the various development methods, as well as the develop inspect that occurs after developing and baking.

 

There are several methods used to develop resist films, and selection of a method is dependent on the resist polarity, the feature size, defect density, the thickness of a layer to be etched, and productivity.  The oldest development method is immersion.  Simply put, the wafers are immersed in a tank of developer solution and then transferred to a rinse tank.  There are numerous problems associated with this method however.  For example, the surface tension of the liquids could prevent the chemicals from penetrating into small openings.  The immersion tanks and wafers can easily become contaminated.  Also, developer chemicals can become diluted through use on numerous wafers. 

 

A preferred chemical development method is spray development.  For this process, fewer chemicals are required, and process improvements include better image definition.  Better definition is achieved by the mechanical action of the spray pressure in defining resist edges and the removal of partially polymerized pieces of resist.  This process is also cleaner then the immersion system since fresh chemicals are used with each wafer.  The spray process can be done either in single or batch systems.  In a single wafer configuration, the wafer is clamped on a vacuum chuck and rotated while first the developer and then the rinse are sprayed onto the surface.  The rotational speed is increased immediately after the rinse cycle to allow for the wafer to dry.  This method has been standard for negative resists, but for temperature sensitive positive resists it is less effective.  The issue is with this method is the phenomenon called adiabatic cooling, which causes the rapid cooling of a fluid dispensed through an orifice under pressure.  To account for this phenomenon, spray developers used for positive resists have a heated wafer chuck or a heated spray nozzle to control the develop temperature.  Batch development is done either by single-boat or multiple-boat.  Batch development systems aren’t as uniform as direct-spray developing. 

 

chipPuddle development is a process used to obtain the benefits of spray development for positive resists.  Puddle development differs from spray development in how the developer chemical is applied to the wafer.  First, enough developer is applied to the wafer to cover the surface.  The puddle sits on the wafer, which is usually on a heated chuck, causing the majority of the development to take place.  After development occurs the wafer is sprayed with more developer, rinsed, dried, and moved along to the next step.

 

To replace liquid chemical developers, the plasma etch process is used.  In this process ions, energized by a plasma field, chemically dissolve exposed layer surfaces.  Dry resist development requires a photoresist chemistry that leaves either the exposed or unexposed portions of the resist layer readily removable by plasma-energized oxygen.  This process is difficult to integrate into automated lines, and the chemicals are more expensive to purchase, store, control, and remove.   

 

After the developing and baking process, a develop inspect is performed.  The goal of this inspection is to identify the wafers that will most likely not pass the final masking inspection.  While the number of wafers that pass this first inspection is not factored into the overall yield formula, it is important for two reasons.  First, wafers can be identified that have issues with the quality of the pattern.  These wafers can be reworked.  Wafers that have problems from other steps that prevent them from continuing are identified and discarded.  During the develop inspect, the wafers are inspected for deviations in the pattern dimensions, misaligned patters, surface problems such as contamination or holes, and patterns that are distorted in shape.  The first inspection is done with the naked eye either in a normal light room, or with a high-intensity ultraviolet light.  Thickness irregularities, gross developing problems, scratches and contamination issues can often be detected.  Wafers that pass this stage are then inspected with a microscope.  However, with processes getting more numerous and more sophisticated, automatic inspection is the inspection system of choice for off-line and on-line inspections.  Automatic inspections offer larger amounts of data that allow the process engineers more control.

 

Van Zant, P. (2000). Microchip fabrication, a practical guid to semiconductor processing. (4th ed.). New York, NY: McGraw-Hill.     

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

Amazing New Materials

 

Below is Dr. Michael Watt's most recent blog, written on the progress being made regarding materials used for photonic devices.

Materials are fundamental to active photonics devices, and there were plenty of developments discussed at Photonics West 2014.

Element Six was happy to talk about progress in making large single-crystal diamond and even larger polycrystalline diamond wafers. Carbon has a number of stable forms; diamond, graphite, nanotubes and amorphous carbon. The Element Six process uses CVD conditions in which diamond and graphite are grown, but any graphite is immediately etched away so that only diamond is left. Done right, a very pure perfect single crystal is grown.

Diamond has two really useful properties (other than inducing loyalty): excellent transparency down to 220nm, and remarkable thermal conductivity. This enables windows for very-high-power CO² lasers used in Cymer’s EUV source, among other applications. These materials are now migrating to applications such as semiconductor laser and diodes, where the devices are very small and the local power density is high. A related example of application migration from high to low(er) tech was the introduction by Nikon of fluoride lenses, originally developed for 193 nm lithography, into smaller lower weight camera lenses.

DiamondImproved low birefringence diamond, left - 10-4, right = 10-7, from Element Six

Aurelian David from Soraa talked about GaN grown on GaN, and homo-epitaxy rather than the standard hetero-epitaxy. The resulting improved crystal quality produced much better LEDs with spectacular 75% wall-plug efficiency. There were several more papers on GaN on large silicon wafers, which is the opposite strategy; large area wafers produce lower costs and live with poorer quality epi. Perhaps the most intriguing is work by Samsung and Seoul National University, where they separate the GaN layer from Silicon at the deposition temperature and avoid all of the stress from differential thermal expansion. They are making real progress on figuring out how to make decent LED, but “decent” is not “best”. It’s rather tacky, but in the cost vs. quality race, there is typically just one winner.

The solar cell is the other major photonics application in which materials are front and center. Silicon is firmly established as the incumbent solution. A team led by Yi Chen, from the University of Illinois at Urbana-Champaign, showed an improved moths-eye anti-reflecting top surface. They used a combined deposition and etch process to create resistant islands that acted as a mask to form pyramids on the cell surface. Perhaps this blog should have been on clever uses for simultaneous deposition and etch.

The best alternative to silicon is CIGS (copper indium gallium selenide), but obtaining consistent performance in volume has been the continuing challenge. A paper at the conference showed the uniformity of spectral output from CIGS cells using a “hyperspatial imaging” microscope. The spectral output was non uniform at the scale of µm’s, typical of crystal sizes. The paper was a good example of the power of the right analytical tool to provide insight.

Also on the solar materials front, but not talked about at Photonics West, “peroskovite” based solar cells have shown remarkable progress in three years. Peroskovite describes a crystal structure, and a particular stoichiometry has been found to have useful solar cell properties as a hole conductor. An absorbed photon creates an electron hole pair and the holes are preferentially conducted away. Because, they do not relay on a diode junction, a much wider range of wavelengths result in current. The remarkable story has been the improvement from 6% to 15% efficiency in three years. This sort of progress is always a very encouraging sign. The progress comes from materials discovery and improving the crystal quality based on growth on a TiO² layer. Because there is no junction diode, the 20% limit for a single junction diode does not apply to these materials so there is plenty of future opportunity. The issue appears to be materials cost, which manufacturing volumes usually fix, and lifetime.

All in all, an intriguing set of developments to keep the materials guys busy; try deposition and etch as the solution to any problem, make sure you can measure the results, and always improve crystal quality.

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

Photoresists in Semiconductor Processing

 

semiconductor chipFor decades photoresists have been used in the printing industry, and in the late 1920s were applied to the printed circuit board (PCB) industry. The technology was adopted by the semiconductor industry when Eastman Kodak and the Shipley Company introduced positive and negative photoresists in the late 1950s.  Below we explore the composition of photoresists and the difference between positive and negative photoresists. 

Photoresist Composition

Photoresists are designed to respond to specific wavelengths of light and various exposing sources.  They are also given specific thermal flow characteristics and formulations to adhere to specific surfaces.   Four ingredients make up photoresists. They are polymers, solvents, sensitizers, and additives.  Light and energy sensitive polymers give the photoresists their photosensitive properties.  In negative photoresists, the polymers are most often the polyisopreme type, while positive photoresists utilize a phenol-formaldehyde polymer.  The polymer’s structure changes from soluble to polymerized, or vice versa, when it comes in contact with the exposure source in the aligner.  A solvent is the largest ingredient by volume in a photoresist, and makes the resist a liquid.  This allows the resist to be applied to the wafer surface as a thin layer.  For negative resists the solvent is xylene, while positive resists use either ethoxyethl acetate or 2-methoxyethyl.  Sensitizers are added to resists to either control or entice certain reactions of the polymer.  They can also be used to broaden or narrow the wavelength response of the photoresist.  Bisazide is used as the sensitizer in negative resists, while diazonaphthoquinones are utilized by positive resists.[i]  Additives are mixed into the resists to achieve specific results.  Some possibilities could include dyes to absorb and control light rays in negative resists, or chemical dissolution inhibitor systems in positive resists.

Negative Photoresists vs Positive Photoresists

Through the mid-1970s, negative resists were dominant in the masking process.  While positive resists had been around for over two decades, they were not often used because of their poor adhesion properties.  By the 1980s, positive resists were more common, but the transition was not simple.  The polarity of the masks had to be switched once positive resists were used, requiring a completely new process.  With a negative resist and a light-field masks, the dimensions in the resist is smaller than the mask/reticle dimensions due to light wrapping around the image.  With a positive resist and a dark-field mask, the diffraction often widens the image.  This change must be considered when the mask/reticle is made as well as during the design of the other masking processes.  Another difference between positive and negative resists relates to oxygen.  Negative resists react to oxygen that is in the atmosphere, which can result in a thinning of the resist film by up to 20%.  Positive resists do not react with oxygen in this way.  Positive resists are more expensive then negative resists, but in some cases the extra cost could be offset by higher yields that positive resist could produce.  The two types of resists differ when it comes to developing characteristics as well.  Negative resists develop in solvents and have a high solubility differential between the polymerized and unpolymerized areas.  During developing, the image dimensions remain fairly constant.  Positive resists on the other hand, have a lower solubility between the polymerized and unpolymerized areas, thus requiring carefully prepared developer solutions and a temperature control process.  Just prior to the completion of the masking process, the photoresist must be removed.  In general, the removal of positive resists is easier and occurs in chemicals that are more environmentally sound.        

 


[i] http://cnx.org/content/m25525/latest/

Van Zant, P. (2000). Microchip fabrication, a practical guid to semiconductor processing. (4th ed.). New York, NY: McGraw-Hill.     

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 

Advances in Roll to Roll Processing

 

Below is a paper written by Glew Engineering Cconsultant, Dr. Michael Watts.  The original paper can be found at www.impattern.com

 

Abstract

Today, there are a number of successful commercial applications that utilize roll to roll processing and almost all involve optics; unpatterned film, patterned film, and devices on film. The largest applications today are in holograms, and brightness enhancement film (BEF) for LCD. Solar cells are rapidly growing. These are mostly made in large captive facilities with their own proprietary equipment, materials and pattern generation capability. World wide roll to roll volume is > 100M meters2 year-1, and generates sales of > $5B. The vast majority of the sales are in BEF film by 3M.

Introduction

This review will discuss roll to roll processing as follows;

History

Technology

Applications

History

Roll to roll optics were started as a means to replicate holograms. Some key dates are;

1974 Stephen Benton invented, and Michael Foster developed, a process for mass production of holograms using a thermal embossing technique.

1983 MasterCard International, Inc. became the first to use hologram technology in bankcard security.

1987 American Bank Note Holographics embossed large area holograms onto a plastic roll and transferred them to a 30-inch wide roll of special aluminum foil. These holograms made the front cover of National Geographic.

1992 3M patents issue on films for high brightness displays. These patents are expiring and has lead to an explosion of interest in alternative solutions for a very large market opportunity.

A detailed history can be found at a number of web sites 1.

Technology

The technologies used in roll to roll processing are very similar to wafer processing.

Deposition

Evaporation, sputtering and chemical vapor deposition (CVD) can all be implemented roll to roll. Multilayer sputtering systems are the most common. The entire roll is loaded into the vacuum system (Figure 1a) and it is relatively easy to sputter (Figure 2b) or evaporate different materials without crosstalk2. This is more difficult in CVD where reactive gas barriers are needed within the vacuum system.

Sputtering System


a) Very large multilayer sputtering system

Schematic of sputtering

a) Very large multilayer sputtering system 

Figure 1 Roll to roll multilayer sputtering system as developed at Southwall Inc2

Patterning

Roll to roll patterning requires the creation of an original, and a working copy that can be formed into a roll. Often intermediate sub- masters are used to protect the original, and allow many working copies with limited life to be made. Depending on the geometry, origination techniques include scanning laser and electron beam pattern generation3, analog holography4, interferometry5, and machining6. The working copies are most often nickel shims fabricated by electroless nickel-plating, although plastic working copies are also widely used. Virtually all the roll to roll manufacturers have captive capacity for making working plates.

Patterning of the roll is constrained by the rolling process on a sheet film. Optical lithography is poorly suited to roll processing because of the depth of field requirement for imaging systems.

Schematic of roll to roll patterning

Figure 2 Schematic of roll to roll patterning techniques7

Gravure and flexographic (offset) printing is the classic technique for rolled materials with a minimum spot size of around 20 um on a non wicking surface7.

Ink jet printers will dispense down to 5 nanograms or a 30 um cube8. On a surface designed for printing there is a roughly 100 um minimum feature size. Both resist and functional materials can be ink jetted.

Screen printing can be used to put down functional materials such as conductors with a 50 um mesh, or a minimum feature size of 150 um9.

Imprint is the technology of choice for fine feature patterning. The surface texture on the working plate is replicated into an imprint material. Thermal imprint has been used for holograms since 1979, mostly for security applications. Originally the holograms were created photographically, today digital holograms are created by multilayer digital pattern generation.

A typical feature size for a hologram is λ/2 and step height of λ/4n, 250 nm and 80nm respectively. These features are easily replicated by thermal imprinting, in which the polymer is heated above it’s Tg, forced into the mold and then cooled to set the pattern. The Chou team at Princeton have reported 6 nm replication with a 10 minute imprint cycle10. As the contact time is reduced, the polymer chains do not relax completely, leading to feature relaxation and loss of edge resolution. The same group have used roll to roll to create 70 nm lines and spaces 70 nm deep (Figure 3), at an imprint speed of 0.01 meters min-1, with a 2 mm contact distance, corresponding to a nominal imprint time of 20 secs11.

AFM

Figure 3 AFM images of thermal roll to roll imprint of 70 nm lines and spaces 11

UV imprint is used by many manufacturers as it offers the finest feature resolution at the highest processing speed. This results from the lower viscosity of the imprint material when it is forced into the imprint mold, UV curing then sets the material. Wavefront Technology, Autotype, Reflexite, and HP Labs have all reported utilizing UV cure roll to roll patterning. HP claim to have shown UV cure imprint with < 100 nm resolution at 5 meters per min12 (Figure 4).

UV roll to roll

Figure 4 UV roll to roll showing 40 nm12
features on 50 um polyimide film

heat reflecting window

Figure 5 A heat refelcting window from Southwall

The resolution limit of UV cure imprint is simply the minimum feature size of the master. For example, Molecular Imprints have reported resolution of 1 nm feature butting errors in UV imprint13.

Direct imprint of a functional material that stays with the device is common low cost strategy. For example, conductors can be screen printed or directly imprinted as in RFID tags, or OLED’s. Organic semiconductors have been directly imprinted using solvents as plastizers to assist in deforming the material7.

Pattern Transfer

If pattern transfer is required there are two choices; dry etch of underlying layers, or deposition on top of the patterned surface. The deposition can be a low angle shadowing or deposition into a hole with subsequent lift of the material around the hole (“lift off”).

Inspection

Inspection is a significant issue for optical films where both performance and cosmetic defects are critical. The performance, such as polarization efficiency, can either be measured directly; or indirectly by thin film interference of the thin film multilayer. Video cameras and machine vision analysis are used for cosmetic defects.

Device inspection is rather more challenging because a defect in the mold, will appear in every device and every device may fail. This sort of “repeating defect” has been a challenge in IC manufacturing that has been solved by using a pellicle to protect the mask. In roll to roll, the device inspection strategy can be either “die to die” when there are multiple copies of the device on each master, or die to database. USDC has funded a project to develop pattern defect inspection14.

Economics

The economic challenge is that the low cost of roll to roll manufacturing can only be exploited if the facility is close to fully utilized. In roll to roll processing the challenge is in the limited variety of products that can be run, and the large capacity of any one facility. The variety of products is limited because the sequence of process steps is fixed. This is in contrast to a typical semiconductor fab, where the individual pieces of automated equipment stand alone, and multiple process sequences are supported. The advantage of multiple process sequencies is that a much larger number of products can be manufactured in the facility helping to keep it fully utilized. The other challenge is that the low cost of roll to roll results from the rapid process time, that means that even more product is need to fully utilize the facility. A stepper will process 100 x 300 mm wafers per hour = 0.1 meters2 min-1, and a 1 meter wide web at 10 meters a min = 10 meters2 min-1 or 100x higher throughput. Therefore an application must have very high volumes and /or large areas to utilize a roll to roll fab supporting a single process sequence. Solar cells and display films are two applications where the devices are large area and the potential markets are also very large.

A further complication is that it can be difficult to ramp early stage volumes economically when you need a large dedicated facility.

Applications

Key volume applications for roll to roll manufacturing will now be described

Unpatterned sheet

The two volume applications are IR reflective films, and polarization reflecting film.

Southwall creates a IR reflective film that can form RU -20 rated window (Figure 5, equal to solid insulating wall)2. The challenge is to make it reflective in the IR, but transparent in the visible. The film is a multilayer thin film stack of conductor and dielectric to form a Fabry-Perot interferometer15 .

The other example is a polarizing reflector film, called “ DBEF” by 3M. This film is one component in a LCD display backlight illustrated in Figure 516. A conventional LCD display consists of two crossed absorbing polarizers sandwiching a liquid crystal layer, along with electrical wiring (Figure 6a). A backlight guide directs light from a source to the back of the LCD. The prism film takes light that emerges from the light guide and directs toward the viewer, increasing brightness. The polarizing “recycling” reflecting film is a relatively poor polarizer that reflects one plane of polarization and transmits the other (Figure 6c). The reflected polarization is then scattered to produce unpolarized light. This is then repolarized, to further enhance the brightness. The net enhancement can be as high as 42%




Figure 6 Brightness Enhancement Films (BEF). a) conventional backlight, b) prism film redirects light towards the viewer, c) polarization reflecting film, reflects one polarization which is then scattered to create unpolarized light which can then be repolarized, increasing brightness.

The polarizing reflecting film (DBEF) consists of a stack of multiple layers of two materials which are coextruded and stretched. One material shows birefringence after stretching, the other does not17. As a result, the film has a multilayer stack with different reflectivity in 2 directions.

Volumes of film are estimated at $1B at $100 a squ meter or 10M squ meters per year.

These two examples of unpatterned films use either a metal / dielectric stack to from a IR reflector, or a birefringent / dielectric stack to form a polarizing reflector. Unpatterned films can also have simple multilayer stacks of dielectrics with different refractive index to form UV reflecting films, or anti-reflecting films.

Patterned sheet

Patterned films are almost all either refractive or diffractive optical elements.

Diffractive elements include; holograms, diffusers, and AR films. Security holograms are probably the most common with OVD Kinegram as one of the original and now leading security hologram supplier. There are a large number of display hologram suppliers, Wavefront make very large holograms up to 1.5 meters wide18.These holograms are phase holograms meaning that height changes of a quarter wave (around 80 nm) in a material with a different refractive index create the interference effects. A typical phase diffraction gratings pattern is shown in Figure 7a19 along with a large area grating is Figure 7b.

crossed grating

a) Crossed grating

large area gratingb) Large area grating

Figure 7 Examples of phase diffractive optical elements19

In security holograms, the height changes are buried in materials so they cannot be peeled apart and copied.

Moths eye films are supplied by a number of vendors including Autotype as shown in Figure 820.The moths eye works by creating a surface layer with graded refractive index that is antireflecting over a wide range of wavelengths. The limitation of moth’s eye film is abrasion resistance and clean-ability.


Figure 8 Moth's eye film20

Figure 9 SEM micrograph of 3M prism film16

Refractive elements include; - brightness enhancing prism film, and lens films,. Brightness enhancement film was discussed earlier in Figure 5. A SEM micrograph of the prisms is shown in Figure 916. Volumes of film are estimated at $2B at $50 a squ meter or 40M squ meters per year.

Devices

Devices manufactured by roll to roll include – Solar, E-ink, OLED, RFID, printed electronics. The only devices that are in significant volume manufacture are solar cells.

Solar Cells

Solar cells are one of the simplest devices, a large pn diode. Figure 10a shows a commercial solar cell film and layer structure21.

flexible solar cells

a)

comparative efficiency

b)

Figure 10 Flexible film solar cells a) design21 and b) comparative efficiency22

The top and bottom source and drain conductors sandwich the photoelectric semiconductor. An array of metal conductors, shown in the photograph of the film in Figure 10a, collect electrons from each region of the cell.

The efficiency of the solar cell is directly linked to quality of the semiconductor22. The very best solar cells are made in epitaxially grown single crystal silicon (cSi in Figure 10b). The majority of commercial cells are made by a lower cost process that creates “multi-crystalline bulk silicon” or mSi solar cells with lower power generation efficiency.

Growing silicon on a thin film substrates is an example of “hetereoepitaxy” and is a much harder challenge. The growth must be done at temperatures that the substrate can tolerate, and the lack of a lattice match produces crystal defects.

The best understood application of silicon heteroepitaxy is in thin film transistors on glass for LCD backplanes. LCD’s use a substrate of borosilicate glass with a melting temperature of 821 C, to allow activation of amorphous silicon and the creation of reliable transistors. Several vendors have developed roll to roll solar cell on stainless steel film substrates with a melting point >1300C. Even so the efficiency of amorphous cell is only 2/3 of a commercial multi-crystalline cell (Figure10b). Amorphous silicon on polyimide sheet must be processed below 400C, and has poorer efficiency. The lower efficiency means that a larger area of cells are required for each watt of power generation. This offsets some of the lower cost advantage. Applied Materials appear to have made a very large commitment to the potential of glass and roll to roll thin film solar cells23.

There is also a lot of interest in alternative semiconductors including complex II/VI alloys such as

Cadmium Indium Gallium diSelenide (CIGS)24, and organic semiconductors.

Photovoltaic solar sales are $6B a year, but only a very small fraction is roll to roll solar. At $5 a watt and 200 watts per squ meter this is equivalent to a potential volume of 6M squ meters a year.

Leading companies in roll to roll solar, include Power Film ex - Iowa Thin Film Technologies, and United Solar who have built a 28 MW capacity plant25. Ascent Solar Technologies, Inc. are a new player26. Equipment suppliers include Applied Materials, General Vacuum Equipment, United Kingdom; Stangl Semiconductor Equipment AG, Germany; Hiranokohnon, Japan, and ITN Energy Systems, Inc., USA. There is a directory numerous companies working in the flexible solar space on the web27.

E ink - roll to roll display

Low cost roll to roll manufacture of displays has been a long term goal. E-ink is a technology for displays that appears to be taking off. Several companies have announced e- books with e-ink displays. E ink is a simple device illustrated in Figure 11.

sheet of microcapsules

a)

e book

b)

Figure 11 E-ink28 a) Sheet of microcapsules filled with pigment b) E-book using E-ink displays

Each pixel is formed by a microcapsule filled with pigment. The pigment is moved to the surface by electrostatic charge. The great advantage is the display is that is bi-stable and requires no power to hold the pigment in place.

There are several commercial implementations, the SiPix device29 uses cups rather than microcapsules. Polymer Vision use an organic semiconductor TFT behind the e-ink30. As in LCD’s, the TFT allows larger pixel count displays and gray scale images.

Organic Light Emitting Diodes (OLED)

OLED’s have started to appear in specialist niche applications such as the external monochrome displays in cell phones where power consumption is critical.

Larger displays have been demonstrated, for example Universal Display Corp. has shown off a full-color

OLED screen that's extremely thin and, more importantly, flexible31.The prototype's screen measures 100 mm diagonal, and is only 0.1 mm thick .The low pixel count displays use multiplexed drive, where the an array of rows and columns are used to address a pn junction in the emitting semiconductor (Figure 13a).

multiplexeda)

active matrixb)

Figure 12 a) Multiplexed and b) Active matrix addressed dislays

Higher resolution full color grey scale displays (Figure 13) use an active matrix of transistors at the intersection of every row and column in an “active matrix display” Figure 12b.

OLED

Figure 13 Example of a full color OLED display from Sony31

A study found that the tooling cost of setting an active-matrix flexible organic light-emitting diode (OLED) substrate line amounted to roughly $2000 per square meter32. The cost of tooling a passive-matrix polymer light-emitting diode (PLED) line is far less, at $500 per square meter.

Printed electronics

Examples of printed electronics include RFID’s, TFT backplanes for displays, and general purpose
devices. RFID’s are a good example of a simple device with a large aerial that can be fabricated at the same time as the drive electronics in a roll to roll process. PolyIC has unveiled two organic "chips" manufactured in an industrial roll-to-roll printing process (Figure 14).


RFID

Figure 14 Printed RFID’s that are large area devices that include both ariel and logic33

One incorporates an RFID chip dubbed PolyID; it is equipped with an integrated 4-bit memory. The other one, PolyLogo, is a display device that is activated when it enters an RF field. The transistors the chips are consisting of have printed feature sizes smaller than 20 microns33.

There have been pioneering efforts by Polymer Vision, Plastic Logic, and HP in creating TFT backplanes. The HP team have described how they have had to build all the equipment everything themselves, which slows down the development cycle32. In addition, innovative process that simplify the equipment requirements are highly desirable. Layer to layer alignment is very challenging in roll to roll because the flexible substrate is easily distorted. HP has developed a self-aligned imprint lithography (SAIL) process, illustrated in Figure 1512.

a) Classic 3 layer process

b) Single 3 layer imprint

SEM

c) SEM of 3 layer imprint

Figure 15 Self Aligned Imprint Process12

A classic 3 layer transistor with source, drain and gate regions is shown in Figure 15a). A single 3 layer imprint for a device is shown in Figure 15b, and an SEM of the imprint in Figure 15c.

A unique sequence of etching of the underling layers with varying undercut, then etching away the resist step is used to create 3 different patterned layers. SAIL solves the alignment problem but creates a need for a unique combination of etch stops, and end point detection technology12.

Particle management and inspection are other open issues for a complete manufacturing process.

Conclusion

Roll to roll processing is a multi billion dollar industry that is uniquely suited to manufacturing very large area devices. Display components are the most common application although device applications are starting to appear.

The quality of the semiconducting material will control the speed of development of commercial device applications.

Manufacturing costs for a single layer are $20-30 per meter2 compared to $150 for a semiconductor process. Costs for multilayer devices are $300 per meter2 for a 5-6 layer device compared to $150 for semiconductors. The higher cost for multilayer devices reflects the immaturity of roll to roll processing. As a result, roll to roll processing dominates in the creation of single layer products and very large multilayer devices.


1 History of Holography at en.wikipedia.org/wiki/BanknoteSource & www.holophile.com/history.htm
2 Southwall Inc. at www.southwall.com
3 Commercial mask houses such as Dai Nippon Screen, Toppan or smaller imprint focused operation such as NILT.
4 Commercial vendors include Kurtz and Holotools. Many of the merchant roll to roll suppliers, such as Wavefront Technologies, have captive hologram origination.
5 Plymouth Gratings at www.plymouthgrating.com and Ref 4.
6 Moore Tools Inc at www.mooretool.com
7 T. Mäkelä et.al. “ A NOVEL IMPRINTING TOOL FOR ROLL TO ROLL MANUFACTURING
OF SUBMICRON STRUCTURES at www.ee.tut.fi/fys/fp2006/proceedings/docs/Oral06-11.pdf
8 See www.inkjetprinter.com
9 See www.crystec.com/joyprie.htm
10 M. D. Austin, W. Zhang, H. X. Ge, D. Wasserman, S. A. Lyon, and S. Y. Chou, "6 nm half-pitch lines and 0.04 mu m(2) static random access memory patterns by nanoimprint lithography," Nanotechnology, 16, 1058, (2005)
11 H Tan et. al. “Roller nanoimprint lithography” J. Vac. Sci. Technol. B 16.6., 1998, 3926
12 www.rle.mit.edu/cips/5_03_06.Taussig2.pdf
13 M. Miller et. al. “Fabrication of Nanometer Sized Features on Non-Flat Substrates Using a Nano-Imprint Lithography Process “, SPIE Microlithography 2005, Proceedings Vol. 5751 Emerging Lithographic Technologies IX, pp.994-1002
14 www.eetimes.com/news/design/showArticle.jhtml?articleID=174401743
15 USP 5,071,206 .
16 3M web site at www.mmm.com
17 USP 7038745
18 www.wavefronttechnology.com
19 Personal communication C. Rich Wavefront Technologies Inc.
20 Z. Gou, K. Parsons, V. Boerner; A Multifunctional Single Layer Anti-Reflection/Anti-Glare Film, SID 2006
21 Powerfilm web site at http://www.powerfilmsolar.com/
22 Solar film efficiencies at www.nre.gov/ncpv/thin_film/docs/kaz_best_research_cells.ppt
23 Applied Materials at www.amat.com
24 M.E. Beck1, I.L. Repins, J.S. Britt “Process Tolerances in Roll-to-Roll Manufacturing of CIGS-Based Photovoltaics on
Flexible Substrates” http://www.nrel.gov/pv/thin_film/docs/gsesolarreview2005.pdf
25 http://www.ovonic.com/eb_so_thin_film_pv_technology_2.cfm.
26 www.allbusiness.com/services/business-services/3998958-1.html
27 http://www.peswiki.com/index.php/Directory:Thin_Film_Solar
28 E-ink at www.eink.com
29 Sci Pix at www.sipix.com/technology/epaper.html
30 Polymer Vision at www.polymervision.com/index.html
31 http://dvice.com/archives/2006/02/new_oled_prototype_is_a_rollup.php
32www.smalltimes.com/display_article/292547/109/ARTCL/none/Tech/Manufacturing_progress_key_to_flexible_electronics%E2%80%99_success/
33 PolyIC at www.polyic.com

For more information on Glew Engineering Consulting visit the Glew Engineering website, blog or call 800-877-5892 or 650-641-3019. 
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Linear v Novellus (Semiconductor Equipment)

  
  

After 8 long years, Novellus finally rid itself of the lawsuit with Linear Technology. Irell and Manella LLP, for whom Glew Engineering has worked in the past, took no prisoners in the unanimous jury verdict announced yesterday in favor of their client Novellus.  The jury consisted of 12 men and women in Santa Clara, CA, the heart of the silicon valley.  Certainly good news for Novellus' legal team, as well as their bottom line. Congratulation to Jonathan Kagan Esq. and his colleagues.  Now both sides can get back to what they do best - making chips and chip equipment.

Novellus' also shipped their 1000th Vector PECVD tool in February? Considering the tool's throughput and uptime, there may be as many chips out there by now with Novellus' dielectric films as those of any semiconductor equipment manufacturer. See the details at: 

http://ir.novellus.com/releasedetail.cfm?ReleaseID=441840

 

Semiconductor Equipment, Glew Engineering

Comments

Its a nice post read on the advantages of the solar energy.Thanks for posting it here.
Posted @ Tuesday, November 01, 2011 4:50 AM by Solar panels georgia
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